146 [fpga] fpga readings
138
- https://github.com/lastweek/fpga_readings
Comments
konosubakonoakua · 2025-02-21T09:07:29Z
courses
- ECE 699 Software/Hardware Codesign Spring 2016
- ECE 6775 High-Level Digital Design Automation Fall 2024
- MIT Introductory Digital Systems laboratory
- 18-643 Course Schedule, Fall 2017 (Not Most Recent)
- https://eclipse.umbc.edu/robucci/cmpe415/
- https://eclipse.umbc.edu/robucci/cmpeRSD/
konosubakonoakua · 2025-02-21T09:18:42Z
Tutorials
- https://zipcpu.com/topics.html
- https://www.realdigital.org/
- https://nandland.com/fpga-101/
- https://www.fpga4fun.com/
- http://www.hellofpga.com/
- https://soc.ustc.edu.cn/Digital/2024/lab0/intro/
- https://github.com/BrunoLevy/learn-fpga
- https://blog.abbey1.org.uk/index.php/technology/fpga/
- https://byu-cpe.github.io/ComputingBootCamp/tutorials/xilinx_deep_dive/
- Official
- https://xilinx.github.io/xup_embedded_system_design_flow/
- https://xilinx.github.io/xup_fpga_vivado_flow/
- https://github.com/Xilinx/axi-packaging-and-linux-driver
- https://github.com/Xilinx/axi_1wire_host-design
- AMD workshops
- https://www.amd.com/en/corporate/university-program/workshops.html
- Alinx
- https://ax7015b-20231-v101.readthedocs.io/zh-cn/latest/index.html
- https://ax7020-20231-v101.readthedocs.io/zh-cn/latest/
- https://ax7z100b-20231-v101.readthedocs.io/zh-cn/latest/index.html
- Digilent
- https://digilent.com/reference/learn/programmable-logic/tutorials/start
- RedPitaya
- http://pavel-demin.github.io/red-pitaya-notes/
- https://learn.redpitaya.com/
- https://redpitaya-knowledge-base.readthedocs.io/en/latest/learn_fpga/fpga_learn.html#learn-fpga
- https://content.redpitaya.com/blog
- https://redpitaya.com/rtd-iframe/?iframe=https://redpitaya.readthedocs.io/en/latest/quickStart/needs.html
- others
- https://github.com/dspsandbox/FPGA-Notes-for-Scientists
konosubakonoakua · 2025-02-24T07:09:33Z
Verilog
- https://asic-world.com/verilog/verilog_one_day.html
- https://www.runoob.com/w3cnote/verilog-tutorial.html
- cmpeRSD discussion01_verilog
konosubakonoakua · 2025-02-26T02:09:51Z
simulator
- https://verilator.org/guide/latest/
- https://gtkwave.github.io/gtkwave/
konosubakonoakua · 2025-02-26T15:45:03Z
misc
- https://beaglewire.github.io/
- xillybus: An FPGA IP core for easy DMA over PCIe with Windows and Linux
konosubakonoakua · 2025-03-05T07:23:02Z
blogs
- Experimenting with Metastability and Multiple Clocks on FPGAs
- adiuvo microzed chornicles
- https://github.com/pavel-demin/red-pitaya-notes
- https://www.wlanxww.com/posts/zynqmp-system/
- https://blog.songshiyu.cn/archives/fpgakai-fa-ya-wen-tai-gai-shu
konosubakonoakua · 2025-03-05T07:26:47Z
videos
- metastability
- How does a flip flop work, what is metastability and why does it have setup & hold time?
- Metastability and Synchronizers
- FPGA #22 - Clock Domains, Metastability, and Synchronizers
- reset
- Which to use , Asynchronous reset or synchronous reset ? Resets Explained || Reset synchronizer!!
- verilog
- 28 - Verilog Behavioral Modeling Coding Guidelines
- axi
- what is axi
- How the AXI-style ready/valid handshake works
- bilibili alltowine dma ddr3 axi ps pl
- misc
- bilibili helowen
konosubakonoakua · 2025-05-07T09:18:30Z
https://tknopp.github.io/RedPitayaDAQServer/dev/index.html
konosubakonoakua · 2025-05-13T08:35:59Z
I/O timing constraints for FPGA/ASIC #4: Source-synchronous output (article, 2025) I/O timing constraints for FPGA/ASIC #3: Sink-synchronous input (article, 2025) I/O timing constraints for FPGA/ASIC #2: System-synchronous input (article, 2025) I/O timing constraints for FPGA/ASIC #1: Source-synchronous input (article, 2025) The many ways to mess up ready/valid handshaking (article, 2024) Reliable FPGA CDC constraints #5: Asynchronous FIFO (article, 2024) Why is CDC so hard? Presentation at CERN (conference talk, 2024) Simulate FPGA design with Vivado simulation libraries (video tutorial, 2024) Reliable FPGA CDC constraints #4: Build tool settings (article, 2024) Reliable FPGA CDC constraints #3: Pulses (article, 2024) Reliable FPGA CDC constraints #2: Counters and FIFOs (article, 2024) Reliable FPGA CDC constraints #1: The simple single-bit level CDC (article, 2024) Real-time stereoscopic object tracking on FPGA using neural networks (master thesis, 2014)